Digital design: principles and practices (2nd ed.)
Digital design: principles and practices (2nd ed.)
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Elementary functions: algorithms and implementation
Elementary functions: algorithms and implementation
Leading-One Prediction with Concurrent Position Correction
IEEE Transactions on Computers
Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers
IEEE Transactions on Computers
Hardware Designs for Exactly Rounded Elementary Functions
IEEE Transactions on Computers
Leading-One Prediction Scheme for Latency Improvement in Single Datapath Floating--Point Adders
ICCD '98 Proceedings of the International Conference on Computer Design
Low-Power Properties of the Logarithmic Number System
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Leading Zero Anticipation and Detection A Comparison of Methods
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
VLSI Implementation of a Low-Power Antilogarithmic Converter
IEEE Transactions on Computers
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition
IEEE Transactions on Computers
A low-power handheld GPU using logarithmic arithmetic and triple DVFS power domains
Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
The processing element design for a large-scale spatio-temporal pattern clustering system
Analog Integrated Circuits and Signal Processing
Journal of Signal Processing Systems
An iterative logarithmic multiplier
Microprocessors & Microsystems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a high precision logarithmic converter in a binary floating point divider
Concurrency and Computation: Practice & Experience
An approximate logarithmic squaring circuit with error compensation for DSP applications
Microelectronics Journal
Hi-index | 14.99 |
This paper presents a unique 32-bit binary-to-binary logarithm converter including its CMOS VLSI implementation. The converter is implemented using combinational logic only and it calculates a logarithm approximation in a single clock cycle. Unlike other complex logarithm correcting algorithms, three unique algorithms are developed and implemented with low-power and fast circuits that reduce the maximum percent errors that result from binary-to-binary logarithm conversion to 0.9299 percent, 0.4314 percent, and 0.1538 percent. Fast 4, 16, and 32-bit leading-one detector circuits are designed to obtain the leading-one position of an input binary word. A 32-word x 5-bit MOS ROM is used to provide 5-bit integers based on the corresponding leading-one position. Both converter area and speed have been considered in the design approach, resulting in the use of a very efficient 32-bit logarithmic shifter in the 32--bit logarithmic converter. The converter is implemented using 0.6\mu{\rm m} CMOS technology, and it requires 1,600\lambda\times 2,800\lambda of chip area. Simulations of the CMOS design for the 32-bit logarithmic converter, operating at {\rm V_{DD}} equal to 5 volts, run at 55 MHz, and the converter consumes 20 milliwatts.