Elementary functions: algorithms and implementation
Elementary functions: algorithms and implementation
The scientist and engineer's guide to digital signal processing
The scientist and engineer's guide to digital signal processing
Hardware Designs for Exactly Rounded Elementary Functions
IEEE Transactions on Computers
Symmetric Bipartite Tables for Accurate Function Approximation
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
Low-Power Properties of the Logarithmic Number System
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Unrestricted Faithful Rounding is Good Enough for Some LNS Applications
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
CMOS VLSI Implementation of a Low-Power Logarithmic Converter
IEEE Transactions on Computers
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition
IEEE Transactions on Computers
A low-power handheld GPU using logarithmic arithmetic and triple DVFS power domains
Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques
Journal of Systems Architecture: the EUROMICRO Journal
An iterative logarithmic multiplier
Microprocessors & Microsystems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An approximate logarithmic squaring circuit with error compensation for DSP applications
Microelectronics Journal
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This paper presents a VLSI implementation of a unique 32-bit antilogarithmic converter, which generates data for some digital-signal-processing (DSP) applications. Novel antilogarithm correcting algorithms are developed and implemented with low-power and hardware-efficient correcting circuits. The VLSI implementations of these algorithms are much smaller than other hardware intensive algorithms found in the literature. The converter is implemented using 0.6 \mum CMOS technology, and its combinational logic implementation requires 1,500\lambda\times2,800\lambda of chip area. The 32-bit antilogarithmic converter computes the antilogarithm in a single clock cycle and runs at 100 MHz and consumes 81 milliwatts.