FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques

Authors:
R. Gutierrez;V. Torres;J. Valls
Affiliations:
Department of Physics and Computer Architecture, Miguel Hernandez University, 03202 Elche, Alicante, Spain;Instituto de Telecomunicaciones y Aplicaciones Multimedia, Universidad Politécnica de Valencia, 46730 Grao de Gandía, Valencia, Spain;Instituto de Telecomunicaciones y Aplicaciones Multimedia, Universidad Politécnica de Valencia, 46730 Grao de Gandía, Valencia, Spain
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2010

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Abstract

This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communications systems where a throughput between 20 and 40MHz is required. The proposed architecture implements a division operation of two inputs by means of a logarithmic transformation, in which the division can be performed with a subtraction. A combination of non-uniform segmentation and multipartite LUT technique is proposed for the arctangent of the logarithm approximation. The architecture was implemented in a Xilinx FPGA device achieving higher throughput than the approach based on CORDIC algorithm and lower area than previous LUT-based approaches.