Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
OFDM Wireless LANs: A Theoretical and Practical Guide
OFDM Wireless LANs: A Theoretical and Practical Guide
Hardware Designs for Exactly Rounded Elementary Functions
IEEE Transactions on Computers
Faithful Bipartite ROM Reciprocal Tables
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Exact Computation of a Sum or Difference with Applications to Argument Reduction
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Faithful Interpolation in Reciprocal Tables
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
New Algorithms for Improved Transcendental Functions on IA-64
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Some Improvements on Multipartite Table Methods
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
High-Performance Architectures for Elementary Function Generation
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Elementary Functions: Algorithms and Implementation
Elementary Functions: Algorithms and Implementation
Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN
Journal of Signal Processing Systems
FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques
Journal of Systems Architecture: the EUROMICRO Journal
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This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture takes advantage of embedded hard-cores of the FPGA device to achieve lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm or conventional LUT-based methods. The proposed architecture can compute the atan(Y/X) with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC or 46% lower than multipartite approach.