High-Performance Architectures for Elementary Function Generation

Authors:
Jun Cao;Belle W. Y. Wei;Jie Cheng
Affiliations:
-;-;-
Venue:
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Year:
2001

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Abstract

Abstract: High-speed elementary function generation is crucial to the performance of many DSP applications. This paper presents three new architectures for generating elementary functions with IEEE single precision using second-order interpolation. These designs have been developed through a combination of architectural innovations and algorithm developments. They represent a range of trade-off between the use of memory modules and computational circuits. Our most memory intensive architecture uses one third less memory than alternative schemes while incurring no time penalty and minimal additional circuitry.