High-performance special function unit for programmable 3-D graphics processors

Authors:
Davide De Caro;Nicola Petra;Antonio G. M. Strollo
Affiliations:
Department of Electronics and Telecommunication Engineering, University of Napoli Federico II, Napoli, Italy;Department of Electronics and Telecommunication Engineering, University of Napoli Federico II, Napoli, Italy;Department of Electronics and Telecommunication Engineering, University of Napoli Federico II, Napoli, Italy
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2009

Citing 15
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Abstract

An high-speed special function unit (SFU) is presented in this paper. The system supports the single-precision IEEE-754 floating-point standard and implements faithfully rounded reciprocal, square root, reciprocal square root, logarithm, and exponential functions. The functions are approximated by using a novel constrained piecewise quadratic interpolation technique. In this way, the lookup table size is reduced by 40% with respect to previously proposed techniques, without any loss in accuracy. Error analysis and sizing methodology are presented in the paper. The SFU has been implemented in a 0.18-µm CMOS technology. The circuit is able to operate up to 420-MHz clock frequency, with a power dissipation of 160 mW at 420 MHz. The system can be employed in programmable graphics accelerators and in other applications where high-performance function evaluation is needed.