A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation
IEEE Transactions on Computers
Parameterized floating-point logarithm and exponential functions for FPGAs
Microprocessors & Microsystems
Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
High-performance special function unit for programmable 3-D graphics processors
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A Novel Cotransformation for LNS Subtraction
Journal of Signal Processing Systems
On the number of segments needed in a piecewise linear approximation
Journal of Computational and Applied Mathematics
High-performance hardware operators for polynomial evaluation
International Journal of High Performance Systems Architecture
Hierarchical segmentation for hardware function evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A dynamic non-uniform segmentation method for first-order polynomial function evaluation
Microprocessors & Microsystems
Faithful single-precision floating-point tangent for FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Floating-Point Exponentiation Units for Reconfigurable Computing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Many general table-based methods for the evaluation in hardware of elementary functions have been published. The bipartite and multipartite methods implement a first-order approximation of the function using only table lookups and additions. Recently, a single-multiplier second-order method of similar inspiration has also been published. This paper extends such methods to approximations of arbitrary order, using adders, small multipliers, and very small ad-hoc powering units. We obtain implementations that are both smaller and faster than previously published approaches. This paper also deals with the FPGA implementation of such methods. Previous work have consistently shown that increasing the approximation degree lead to not only smaller but also faster designs, as the reduction of the table size meant a reduction of its lookup time, which compensated for the addition and multiplication time. The experiments in this paper suggest that this still holds when going from order 2 to order 3, but no longer when using higherorder approximations, where a tradeoff appears.