Elementary functions: algorithms and implementation
Elementary functions: algorithms and implementation
Arithmetic on the European Logarithmic Microprocessor
IEEE Transactions on Computers - Special issue on computer arithmetic
Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit
IEEE Transactions on Computers
IEEE Transactions on Computers
MiniBit: bit-width optimization via affine arithmetic
Proceedings of the 42nd annual Design Automation Conference
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Table-based polynomials for fast hardware function evaluation
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis
IEEE Transactions on Computers
Energy-efficient image compression for resource-constrained platforms
IEEE Transactions on Image Processing
Optimization of imprecise circuits represented by Taylor series and real-valued polynomials
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis
Journal of Signal Processing Systems
Hierarchical segmentation for hardware function evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of multi-mode application-specific cores based on high-level synthesis
Integration, the VLSI Journal
A dynamic non-uniform segmentation method for first-order polynomial function evaluation
Microprocessors & Microsystems
Small gestures go a long way: how many bits per gesture do recognizers actually need?
Proceedings of the Designing Interactive Systems Conference
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We present an automated bit-width optimization methodology for polynomial-based hardware function evaluation. Due to the analytical nature of the approach, overflow protection and precision accurate to one unit in the last place (ulp) can be guaranteed. A range analysis technique based on computing the root of the derivative of a signal is utilized to determine the minimal number of integer bits. Fractional bit requirements are established using an analytical error expression derived from the functions that occur along the data path. Global fractional bit optimization across multiple computation stages is performed using simulated annealing and circuit area estimation functions.