IEEE Transactions on Computers
Elementary functions: algorithms and implementation
Elementary functions: algorithms and implementation
Approximating Elementary Functions with Symmetric Bipartite Tables
IEEE Transactions on Computers
Arithmetic on the European Logarithmic Microprocessor
IEEE Transactions on Computers - Special issue on computer arithmetic
The Symmetric Table Addition Method for Accurate Function Approximation
Journal of VLSI Signal Processing Systems
A 20 Bit Logarithmic Number System Processor
IEEE Transactions on Computers
Fast Evaluation of the Elementary Functions in Single Precision
IEEE Transactions on Computers
Multipartite Tables in JBits for the Evaluation of Functions on FPGAs
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Function Evaluation by Table Look-up and Addition
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Faithful Bipartite ROM Reciprocal Tables
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Improved Table Lookup Algorithms for Postscaled Division
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Some Improvements on Multipartite Table Methods
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation
IEEE Transactions on Computers
Numerical Function Generators Using LUT Cascades
IEEE Transactions on Computers
A compact and accurate Gaussian variate generator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-performance special function unit for programmable 3-D graphics processors
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A Novel Cotransformation for LNS Subtraction
Journal of Signal Processing Systems
On the number of segments needed in a piecewise linear approximation
Journal of Computational and Applied Mathematics
High-performance hardware operators for polynomial evaluation
International Journal of High Performance Systems Architecture
Function approximation based on estimated arithmetic operators
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Hierarchical segmentation for hardware function evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A dynamic non-uniform segmentation method for first-order polynomial function evaluation
Microprocessors & Microsystems
Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA
Integration, the VLSI Journal
| Hi-index | 14.99 |
A unified view of most previous table-lookup-and-addition methods (bipartite tables, SBTM, STAM, and multipartite methods) is presented. This unified view allows a more accurate computation of the error entailed by these methods, which enables a wider design space exploration, leading to tables smaller than the best previously published ones by up to 50 percent. The synthesis of these multipartite architectures on Virtex FPGAs is also discussed. Compared to other methods involving multipliers, the multipartite approach offers the best speed/area tradeoff for precisions up to 16 bits. A reference implementation is available at www.ens-lyon.fr/LIP/Arenaire/.