IEEE Transactions on Computers
Scientific Simulations with Special Purpose Computers: The Grade Systems
Scientific Simulations with Special Purpose Computers: The Grade Systems
Arithmetic Co-Transformations in the Real and Complex Logarithmic Number Systems
IEEE Transactions on Computers
Matrix Engine for Signal Processing Applications Using the Logarithmic Number System
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Function Evaluation by Table Look-up and Addition
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Design of a Faithful LNS Interpolator
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
IEEE Transactions on Computers
A Comparison of Floating Point and Logarithmic Number Systems for FPGAs
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Table-based polynomials for fast hardware function evaluation
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
The UCSC Kestrel Application-Unspecific Processor
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Array Processing Using Alternate Arithmetic - A 20 Year Legacy
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic
Journal of VLSI Signal Processing Systems
Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Optimizing Logarithmic Arithmetic on FPGAs
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Sign/Logarithm Arithmetic for FFT Implementation
IEEE Transactions on Computers
The Sign/Logarithm Number System
IEEE Transactions on Computers
The European Logarithmic Microprocesor
IEEE Transactions on Computers
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The Logarithmic Number System (LNS) can be considered a simplification of the Floating Point (FP) Number System that assumes the mantissa is always equal to one, and has a binary fixed-point exponent. LNS converts multiplication/division to a single addition/subtraction, which make LNS a very attractive choice for applications where these operations predominate, such as in some signal-processing algorithms. However, for wordlengths greater than 20 bits LNS becomes expensive because of the hardware-demanding LNS operations of addition and subtraction, which are typically important for most signal-processing algorithms. This paper gives an overview of the family of LNS subtraction algorithms called "Cotransformations," and proposes a "Novel Cotransformation Combination" that offers improvements in terms of area and speed without sacrificing accuracy compared to previous methods. The hardware requirements of the proposed method are analyzed mathematically, and the results are verified by using synthesis and simulations.