A Comparison of Floating Point and Logarithmic Number Systems for FPGAs

Authors:
Michael Haselman;Michael Beauchamp;Aaron Wood;Scott Hauck;Keith Underwood;K. Scott Hemmert
Affiliations:
University of Washington;University of Washington;University of Washington;University of Washington;Sandia National Labratories;Sandia National Labratories
Venue:
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2005

Citing 0
Cited 6

A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic

Journal of VLSI Signal Processing Systems
Performance and accuracy of hardware-oriented native-, emulated-and mixed-precision solvers in FEM simulations

International Journal of Parallel, Emergent and Distributed Systems
A Novel Cotransformation for LNS Subtraction

Journal of Signal Processing Systems
GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems

ACM Transactions on Embedded Computing Systems (TECS)
Design of a high precision logarithmic converter in a binary floating point divider

Concurrency and Computation: Practice & Experience
Accelerating ncRNA homology search with FPGAs

Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

Quantified Score

Hi-index	0.00

Visualization

Abstract

There have been many papers proposing the use of logarithmic numbers (LNS) as an alternative to floating point because of simpler multiplication, division and exponentiation computations[1,4-9,13]. However, this advantage comes at the cost of complicated, inexact addition and subtraction, as well as the need to convert between the formats. In this work, we created a parameterized LNS library of computational units and compared them to an existing floating point library. Specifically, we considered multiplication, division, addition, subtraction, and format conversion to determine when one format should be used over the other and when it is advantageous to change formats during a calculation.