Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
A 20 Bit Logarithmic Number System Processor
IEEE Transactions on Computers
SRT Division Architectures and Implementations
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
CMOS VLSI Implementation of a Low-Power Logarithmic Converter
IEEE Transactions on Computers
A Comparison of Floating Point and Logarithmic Number Systems for FPGAs
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
IEEE Transactions on Computers
Low-power 3D graphics processors for mobile terminals
IEEE Communications Magazine
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In most floating-point operations related with 3D graphic applications for mobile devices, properly approximated data calculations with reduced complexity and low power are preferable to exactly rounded floating-point operations with unnecessary preciseness of cost. Among all the sophisticated floating-point arithmetic operations, division is the most complicated and time consuming. We adopted the concept of the logarithmic number system and proposed a novel approach of designing a hardware logarithm converter to utilize the advantage of the transformation of the division into a simple subtraction. The proposed piecewise interpolation method with differential coefficients for logarithmic conversion greatly reduces the error range compared with the previous studies. The comparison between our divider and the conventional precision divider shows that the throughput has been considerably improved with slightly increased gate counts, where the difference of the results is sufficiently tolerable for mobile 3D graphic applications. Copyright © 2010 John Wiley & Sons, Ltd.