Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
IEEE Transactions on Computers
Redundant Logarithmic Arithmetic
IEEE Transactions on Computers
A Hybrid Number System Processor with Geometric and Complex Arithmetic Capabilities
IEEE Transactions on Computers
Applying Aeatures of IEEE 754 to Sign/Logarithm Arithmetic
IEEE Transactions on Computers - Special issue on computer arithmetic
Implementation of Four Common Functions on an LNS Co-Processor
IEEE Transactions on Computers
Semi-Logarithmic Number Systems
IEEE Transactions on Computers
The logarithmic number system for strength reduction in adaptive filtering
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Arithmetic on the European Logarithmic Microprocessor
IEEE Transactions on Computers - Special issue on computer arithmetic
Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit
IEEE Transactions on Computers
Arithmetic Co-Transformations in the Real and Complex Logarithmic Number Systems
IEEE Transactions on Computers
Logarithmic Number System for Low-Power Arithmetic
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
IEEE Transactions on Computers
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition
IEEE Transactions on Computers
A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic
Journal of VLSI Signal Processing Systems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a high precision logarithmic converter in a binary floating point divider
Concurrency and Computation: Practice & Experience
Low-power digital filtering based on the logarithmic number system
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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The architecture and performance of a 20-bit arithmetic processor based on the logarithmic number system (LNS) is described. The processor performed LNS multiplication and division rapidly and with a low hardware complexity. Addition and subtraction in the LNS require the support of a table lookup unit. A scheme is proposed to minimize this complexity using a partitioned memory (ROM) and a PLA (programmable logic array). For performance evaluation, the target technology is integrated Schottky logic. The processor is shown to compare well with, if not to outperform, existing floating point (FLP) processors of equivalent range and precision. The speed-power-product ratio of an equivalent FLP processor, compared with that of the LNS processor, is reported to be 20 to 1 in the case of the square and square-root operation and 1 to 1 in the case of addition and subtraction. For multiplication and division, this ratio is about 5 to 1.