Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array
IEEE Transactions on Computers
An Interpolating Memory Unit for Function Evaluation: Analysis and Design
IEEE Transactions on Computers
IEEE Transactions on Computers
Redundant Logarithmic Arithmetic
IEEE Transactions on Computers
A Hybrid Number System Processor with Geometric and Complex Arithmetic Capabilities
IEEE Transactions on Computers
Applying Aeatures of IEEE 754 to Sign/Logarithm Arithmetic
IEEE Transactions on Computers - Special issue on computer arithmetic
A 20 Bit Logarithmic Number System Processor
IEEE Transactions on Computers
Arithmetic on the European Logarithmic Microprocessor
IEEE Transactions on Computers - Special issue on computer arithmetic
IEEE Transactions on Computers - Special issue on computer arithmetic
Arithmetic Co-Transformations in the Real and Complex Logarithmic Number Systems
IEEE Transactions on Computers
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition
IEEE Transactions on Computers
A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation
IEEE Transactions on Computers
Numerical Function Generators Using LUT Cascades
IEEE Transactions on Computers
Hierarchical segmentation for hardware function evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A dynamic non-uniform segmentation method for first-order polynomial function evaluation
Microprocessors & Microsystems
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This paper describes a new method for polynomial interpolation in hardware, with advantages demonstrated by its application to an accurate logarithmic number system (LNS) arithmetic unit. The use of an interleaved memory reduces storage requirements by allowing each stored function value to be used in interpolation across several segments. This strategy can be shown to always use fewer words of memory than an optimized polynomial with stored polynomial coefficients. Interleaved memory function interpolators are then applied to the specific goal of an accurate logarithmic number system arithmetic unit. Many accuracy requirements for the LNS arithmetic unit are possible. Although a round to nearest would be desirable, it cannot be easily achieved. The goal suggested is to insure that the worst case LNS relative error is smaller than the worst case floating point (FP) relative error. Using the interleaved memory interpolator, the detailed design of an LNS arithmetic unit is performed using a second order polynomial interpolator including approximately 91K bits of ROM. This arithmetic unit has better accuracy and less complexity than previous LNS units.