Applying Aeatures of IEEE 754 to Sign/Logarithm Arithmetic
IEEE Transactions on Computers - Special issue on computer arithmetic
Numerical Recipes in Pascal: The Art of Scientific Computing
Numerical Recipes in Pascal: The Art of Scientific Computing
A 20 Bit Logarithmic Number System Processor
IEEE Transactions on Computers
Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit
IEEE Transactions on Computers
Arithmetic Co-Transformations in the Real and Complex Logarithmic Number Systems
IEEE Transactions on Computers
Symmetric Bipartite Tables for Accurate Function Approximation
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
A 32-Bit Logarithmic Arithmetic Unit and its Performance Compared to Floating-Point
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Corrections to 'Arithmetic on the European Logarithmic Microprocessor'
IEEE Transactions on Computers
Implementation of (Normalised) RLS Lattice on Virtex
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Logarithmic Number System and Floating-Point Arithmetics on FPGA
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
An Exponentiation Unit for an OpenGL Lighting Engine
IEEE Transactions on Computers
IEEE Transactions on Computers
Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation
IEEE Transactions on Computers
A low-power handheld GPU using logarithmic arithmetic and triple DVFS power domains
Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic
Journal of VLSI Signal Processing Systems
Proposal to improve data format conversions for a hybrid number system processor
ICCOMP'07 Proceedings of the 11th WSEAS International Conference on Computers
Implementation of the least-squares lattice with order and forgetting factor estimation for FPGA
EURASIP Journal on Advances in Signal Processing
GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Hierarchical segmentation for hardware function evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A dynamic non-uniform segmentation method for first-order polynomial function evaluation
Microprocessors & Microsystems
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A new European research project aims to develop a microprocessor based on the logarithmic number system, in which a real number is represented as a fixed-point logarithm. Multiplication and division therefore proceed in minimal time with no rounding error. However, the system can only offer an overall advantage over floating-point if addition and subtraction can be performed with speed and accuracy at least equal to that of floating-point, but these operations require the interpolation of a nonlinear function which has hitherto been either time-consuming or inaccurate. We present a procedure by which additions and subtractions can be performed rapidly and accurately and show that these operations are thereby competitive with their floating-point equivalents. We then present some large-scale case studies which show that the average performance of the LNS exceeds floating-point, in terms of both speed and accuracy.