Applying Aeatures of IEEE 754 to Sign/Logarithm Arithmetic
IEEE Transactions on Computers - Special issue on computer arithmetic
Arithmetic on the European Logarithmic Microprocessor
IEEE Transactions on Computers - Special issue on computer arithmetic
A 32-Bit Logarithmic Arithmetic Unit and its Performance Compared to Floating-Point
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
The Sign/Logarithm Number System
IEEE Transactions on Computers
FPGA Implementation of a Lattice Quantum Chromodynamics Algorithm Using Logarithmic Arithmetic
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Journal of VLSI Signal Processing Systems
A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic
Journal of VLSI Signal Processing Systems
International Journal of Parallel, Emergent and Distributed Systems
Implementation of the least-squares lattice with order and forgetting factor estimation for FPGA
EURASIP Journal on Advances in Signal Processing
Accelerating seismic computations using customized number representations on FPGAs
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
A truly two-dimensional systolic array FPGA implementation of QR decomposition
ACM Transactions on Embedded Computing Systems (TECS)
GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
High-throughput bayesian computing machine with reconfigurable hardware
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Parallel implementation of Cholesky LLT-algorithm in FPGA-based processor
PPAM'07 Proceedings of the 7th international conference on Parallel processing and applied mathematics
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A cyclic scheduling problem with an undetermined number of parallel identical processors
Computational Optimization and Applications
Mathematical and Computer Modelling: An International Journal
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An introduction to a logarithmic number system (LNS) is presented. Range and precision of this arithmetic is briefly discussed. We show that the LNS arithmetic is suitable for a FPGA implementation. A case study will compare parameters of our LNS arithmetic library to a conventional floating-point arithmetic.