Proceedings of the third international conference on Graphs and optimization
Scheduling Computer and Manufacturing Processes
Scheduling Computer and Manufacturing Processes
Local search algorithms for a single-machine scheduling problem with positive and negative time-lags
Discrete Applied Mathematics - Special issue on the combinatorial optimization symposium
A Constraint-Based Method for Project Scheduling with Time Windows
Journal of Heuristics
Logarithmic Number System and Floating-Point Arithmetics on FPGA
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Dynamic reconfiguration in FPGA-based SoC designs (abstract only)
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Minimizing makespan for a bipartite graph on a single processor with an integer precedence delay
Operations Research Letters
| Hi-index | 0.00 |
This paper is motivated by existing architectures of field programmable gate arrays (FPGAs). To facilitate the design process we present an optimal scheduling algorithm using a very universal framework, where tasks are constrained by precedence delays and relative deadlines. The precedence relations are given by an oriented graph, where tasks are represented by nodes. Edges in the graph are related either to the minimum time or to the maximum time elapsed between the start times of the tasks. This framework is used to model the runtime dynamic reconfiguration, synchronization with an on-chip processor and simultaneous availability of arithmetic units and SRAM memory. The NPhard problem of finding an optimal schedule satisfying the timing and resource constraints while minimizing the makespan Cmax, is solved using two approaches. The first one is based on Integer Linear Programming and the second one is implemented as a Branch and Bound algorithm. Experimental results show the efficiency comparison of the ILP and Branch and Bound solutions.