A 32-Bit Logarithmic Arithmetic Unit and its Performance Compared to Floating-Point

Arithmetic on the European Logarithmic Microprocessor

IEEE Transactions on Computers - Special issue on computer arithmetic

Pipelined Computation of Very Large Word-Length LNS Addition/Subtraction with Polynomial Hardware Cost

IEEE Transactions on Computers - Special issue on computer arithmetic

Implementation of (Normalised) RLS Lattice on Virtex

FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications

Logarithmic Number System and Floating-Point Arithmetics on FPGA

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications

GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems

ACM Transactions on Embedded Computing Systems (TECS)