IEEE Transactions on Computers
Computer arithmetic algorithms
Computer arithmetic algorithms
Redundant Logarithmic Arithmetic
IEEE Transactions on Computers
A Hybrid Number System Processor with Geometric and Complex Arithmetic Capabilities
IEEE Transactions on Computers
Implementation of Four Common Functions on an LNS Co-Processor
IEEE Transactions on Computers
Semi-Logarithmic Number Systems
IEEE Transactions on Computers
Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit
IEEE Transactions on Computers
Complex Logarithmic Number System Arithmetic Using High-Radix Redundant CORDIC Algorithms
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
A 32-Bit Logarithmic Arithmetic Unit and its Performance Compared to Floating-Point
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
On-line algorithms for the design of pipeline architectures
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Pipelined Computation of LNS Addition/Subtraction with Very Small Lookup Tables
ICCD '98 Proceedings of the International Conference on Computer Design
Error Analysis of the Kmetz/Maenner Algorithm
Journal of VLSI Signal Processing Systems
Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor
Proceedings of the 17th ACM Great Lakes symposium on VLSI
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A novel pipelined method is proposed to compute the addition/subtraction in very large word-length logarithmic number system (LNS) arithmetic. Digit-parallel additive-normalization and digit on-line multiplicative-normalization methods are adopted to compute the exponential and logarithmic functions, respectively, in LNS addition/subtraction. These two methods can both be implemented in a pipelined and regular architecture. The size of the required lookup tables is now proportional to a third-order polynomial function, instead of an exponential function, of the word length. The total size of the tables in a 32-bit LNS unit is estimated to be less than 53.5 kbits and the total size of the tables in a 64-bit LNS unit will be less than 471 kbits. Furthermore, the hardware cost of the other circuits in the proposed LNS unit is only proportional to the square of the word length. This study also develops a simple leading-zero-bits prediction technique that can significantly enhance the precision in LNS addition/subtraction computation. When compared to floating-point arithmetic design, our approach still suffers from large hardware cost and pipeline latency. However, the proposed approach has provided a theoretical advancement in the development of very large word-length LNS arithmetic.