Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array
IEEE Transactions on Computers
A 20 Bit Logarithmic Number System Processor
IEEE Transactions on Computers
Applying Aeatures of IEEE 754 to Sign/Logarithm Arithmetic
IEEE Transactions on Computers - Special issue on computer arithmetic
Implementation of Four Common Functions on an LNS Co-Processor
IEEE Transactions on Computers
The logarithmic number system for strength reduction in adaptive filtering
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
IEEE Transactions on Computers - Special issue on computer arithmetic
Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit
IEEE Transactions on Computers
Arithmetic Co-Transformations in the Real and Complex Logarithmic Number Systems
IEEE Transactions on Computers
IEEE Transactions on Computers
Gradual and tapered overflow and underflow: a functional differential equation and its approximation
Applied Numerical Mathematics - The third international conference on the numerical solutions of volterra and delay equations, May 2004, Tempe, AZ
A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic
Journal of VLSI Signal Processing Systems
Improving 2D-log-number-system representations by use of an optimal base
EURASIP Journal on Advances in Signal Processing
Gradual and tapered overflow and underflow: A functional differential equation and its approximation
Applied Numerical Mathematics
A Novel Cotransformation for LNS Subtraction
Journal of Signal Processing Systems
| Hi-index | 14.99 |
An architecture is described for performing addition and subtraction of numbers in the logarithmic number system using small lookup tables. Previous implementations require approximately 4*2/sup F/ words for F bits of precision in the fraction. The author shows how to reduce the size of the lookup table to fewer than (18+F)*2/sup F/2/ words. The key to this is the use of a linear approximation of the nonlinear functions stored in the lookup tables. The functions involved are highly nonlinear in some regions, so variable size regions are used for the approximation. The replacement of the F exponential dependence on the number of words by F/2 allows roughly 50% more bits of fractional precision to be obtained for a given amount of ROM. The architecture is mathematically analyzed, yielding explicit expressions for all design parameters. The approach is illustrated with an example logarithmic addition and subtraction unit using 32-b words with 30-b exponents containing 22 fractional bits. A factor of 118 reduction in table size compared to previous techniques is achieved for this example.