An Interpolating Memory Unit for Function Evaluation: Analysis and Design
IEEE Transactions on Computers
IEEE Transactions on Computers
An Algorithm for the Computation of Binary Logarithms
IEEE Transactions on Computers
A Hybrid Number System Processor with Geometric and Complex Arithmetic Capabilities
IEEE Transactions on Computers
Implementation of Four Common Functions on an LNS Co-Processor
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
A 20 Bit Logarithmic Number System Processor
IEEE Transactions on Computers
Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit
IEEE Transactions on Computers
Hi-index | 15.00 |
The design algorithm of a differential group programmable logic array (DGPLA) to generate the precise binary logarithm function is suggested. It can reach an optimal condition such that the number of bits in a PLA is minimized, while the error is still kept as small as possible. Thus, the space in the PLA is saved, estimated at only 15.94 percent of the space for a readonly memory (ROM) counterpart.