Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array
IEEE Transactions on Computers
Computer architecture and organization; (2nd ed.)
Computer architecture and organization; (2nd ed.)
An Interpolating Memory Unit for Function Evaluation: Analysis and Design
IEEE Transactions on Computers
Discrete-time signal processing
Discrete-time signal processing
A 20 Bit Logarithmic Number System Processor
IEEE Transactions on Computers
IEEE Transactions on Computers - Special issue on computer arithmetic
Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit
IEEE Transactions on Computers
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition
IEEE Transactions on Computers
A low-power handheld GPU using logarithmic arithmetic and triple DVFS power domains
Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
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The architecture, design, and performance of a hybrid number system processor are described. The processor performs multiplication, division, square root, and square in the logarithmic number system (LNS) domain. However, the input, output, addition, and subtraction are all executed in the 32-b IEEE standard floating-point number system. With the LNS multiplier and pipelined architecture, the processor is able to perform the geometric and complex arithmetic very effectively. The processor is also shown to compare well to an existing 32-b floating-point DSP (digital signal processor) chip. For the same level of CMOS technology, the performance ratios between the hybrid number system and the floating-point processor are shown to be 6.4:1 and 8:1 for division and square root, respectively; for the complex FFT (fast Fourier transform) algorithm, the ratio is around 2:1.