IEEE Transactions on Computers
Adaptive system identification and signal processing algorithms
Adaptive system identification and signal processing algorithms
Signal coding and processing (2nd ed.)
Signal coding and processing (2nd ed.)
Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Adaptive filter theory (3rd ed.)
Adaptive filter theory (3rd ed.)
Matrix computations (3rd ed.)
Low-power adaptive filter architectures via strength reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Survey of low power techniques for ROMs
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Low power multiplication for FIR filters
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm
IEEE Transactions on Computers
Low-power architectural optimizations for 3D graphics subsystems
Low-power architectural optimizations for 3D graphics subsystems
Low Power Digital CMOS Design
A 20 Bit Logarithmic Number System Processor
IEEE Transactions on Computers
Discrete Lagrangian Method for Optimizing the Design of Multiplierless QMF Filter Banks
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Low Power CORDIC Implementation Using Redundant Number Representation
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Efficient Implementation of Rotation Operations for High Performance QRD-RLS Filtering
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Power-Delay Characteristics of CMOS Multipliers
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
System level power analysis
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Error Analysis of the Kmetz/Maenner Algorithm
Journal of VLSI Signal Processing Systems
| Hi-index | 0.00 |
An important technique for reducing pow er consumption in VLSI systems is strength reduction, the substitution of a less-costly operation such as a shift, for a more-costly operation such a multiplication. Using a logarithmic number represen tation provides sev eral opportunities for strength reductions; in particular, m ultiplicationis performed as the fixed-point addition of logarithms, and extracting a square root is implemented via a shift. These reductions occur transparently at the hardware level; consequently relativ ely little algorithmic modification is required, and they are readily applicable to adaptive filtering. For performing Givens rotations in the QR decomposition recursiv e least squares adaptive filter, logarithmic arithmetic is shown to compare favorably to other strength reduction techniques, such as CORDIC arithmetic, in terms of switched capacitance and numerical accuracy.