The logarithmic number system for strength reduction in adaptive filtering
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
ACM Transactions on Computer Systems (TOCS)
Modified booth truncated multipliers
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Application of Binary Translation to Java Reconfigurable Architectures
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Proceedings of the 42nd annual Design Automation Conference
Full-custom VLSI design of a unified multiplier for elliptic curve cryptography on RFID tags
Inscrypt'09 Proceedings of the 5th international conference on Information security and cryptology
Precision selection for energy-efficient pixel shaders
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Low power Wallace multiplier design based on wide counters
International Journal of Circuit Theory and Applications
Program-based dynamic precision selection framework with a dual-mode unified shader for mobile GPUs
Computers and Electrical Engineering
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The multiplier of a S/390 CMOS microprocessor is described. It is implemented in an aggressive static CMOS technology with 0.20 \mum effective channel length. The multiplier has been demonstrated in a single-image shared-memory multiprocessor at frequencies ...