Novel Radix Finite Field Multiplier for GF(2^m)
Journal of VLSI Signal Processing Systems
The role of custom design in ASIC Chips
Proceedings of the 37th Annual Design Automation Conference
A Scalable and Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m)
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable Dual-Field Elliptic Curve Cryptographic Processor
IEEE Transactions on Computers
Power-Delay Characteristics of CMOS Multipliers
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
VLSI Architecture for Datapath Integration of Arithmetic Over GF(2M) on Digital Signal Processors
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
Guide to Elliptic Curve Cryptography
Guide to Elliptic Curve Cryptography
Explaining the gap between ASIC and custom power: a custom perspective
Proceedings of the 42nd annual Design Automation Conference
ARITH '07 Proceedings of the 18th IEEE Symposium on Computer Arithmetic
PRESENT: An Ultra-Lightweight Block Cipher
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Ultra-Lightweight Implementations for Smart Devices --- Security for 1000 Gate Equivalents
CARDIS '08 Proceedings of the 8th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Elliptic-Curve-Based Security Processor for RFID
IEEE Transactions on Computers
A low-resource public-key identification scheme for RFID tags and sensor nodes
Proceedings of the second ACM conference on Wireless network security
ECC Is Ready for RFID --- A Proof in Silicon
Selected Areas in Cryptography
Privacy-aware multi-context RFID infrastructure using public key cryptography
NETWORKING'07 Proceedings of the 6th international IFIP-TC6 conference on Ad Hoc and sensor networks, wireless networks, next generation internet
ASIACRYPT'07 Proceedings of the Advances in Crypotology 13th international conference on Theory and application of cryptology and information security
Lightweight cryptography and RFID: tackling the hidden overheads
ICISC'09 Proceedings of the 12th international conference on Information security and cryptology
RFID security and privacy: a research survey
IEEE Journal on Selected Areas in Communications
A hardware processor supporting elliptic curve cryptography for less than 9 kGEs
CARDIS'11 Proceedings of the 10th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
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The question of whether elliptic curve cryptography (ECC) can be implemented efficiently enough to meet the strict power and area constraints of passive RFID tags has received considerable attention in recent years. While numerous algorithmic and architectural approaches for reducing the footprint of ECC hardware have been investigated, the potential of full-custom VLSI design is still completely unexplored. In this paper we present the design of a radix-2 and a radix-4 version of a unified (16 × 16)-bit multiplier with a 40-bit accumulator that provides all the arithmetic functionality needed to perform ECC over prime and binary fields. The term "unified" means that our multiply/accumulate (MAC) unit uses the same datapath for the multiplication of integers as well as binary polynomials. We designed a full-custom layout of both the radix-2 and the radix-4 multiplier on basis of a conventional array architecture. Simulation of netlists showed a power saving of 22% and an energy-delay advantage of 48% for the radix-4 multiplier compared to the radix-2 version. The multiplication of binary polynomials consumes about 39% less power than integer multiplication.