A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases
IEEE Transactions on Computers
A New Bit-Serial Systolic Multiplier Over GF(2/sup m/)
IEEE Transactions on Computers
Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)
IEEE Transactions on Computers - Special issue on computer arithmetic
Bit-level systolic arrays for finite-field multiplications
Journal of VLSI Signal Processing Systems
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
GF(2m) Multiplication and Division Over the Dual Basis
IEEE Transactions on Computers
A digit-serial multiplier for finite field GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast elliptic curve cryptography on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Full-custom VLSI design of a unified multiplier for elliptic curve cryptography on RFID tags
Inscrypt'09 Proceedings of the 5th international conference on Information security and cryptology
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In this paper, a new {\it High-Radix} Finite Field multiplicationalgorithm for GF(2^m) is proposed for the first time. The proposedmultiplication algorithm can operate in a Digit-serial fashion, andhence can give a trade-off between the {\it speed}, the{\it area}, the input/outputpin limitation, and the low power consumption by simply {\it varying} the digit size. A detailed example of a new Radix-16GF(2^m) Digit-Serial multiplication architectureadopting the proposed algorithm illustrates a speed improvement of75% when compared to conventional Radix-2 bit-serial realization.This is made more significant when it is noted that the speedimprovement of 75% was achieved at the expense of only 2.3 timesincrease in the hardware requirements of the proposed architecture.