VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Novel Radix Finite Field Multiplier for GF(2^m)
Journal of VLSI Signal Processing Systems
Efficient Multiplier Architectures for Galois Fields GF(24n)
IEEE Transactions on Computers
Low-Energy Digit-Serial/Parallel Finite Field Multipliers
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases
IEEE Transactions on Computers
Fast Arithmetic for Public-Key Algorithms in Galois Fields with Composite Exponents
IEEE Transactions on Computers
New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)
IEEE Transactions on Computers
A New Construction of Massey-Omura Parallel Multiplier over GF(2^{m})
IEEE Transactions on Computers
On Computing Multiplicative Inverses in GF(2/sup m/)
IEEE Transactions on Computers
GF(2m) Multiplication and Division Over the Dual Basis
IEEE Transactions on Computers
Efficient Bit Serial Multiplication Using Optimal Normal Bases of Type II in GF (2m)
ISC '02 Proceedings of the 5th International Conference on Information Security
Redundant Representation of Finite Fields
PKC '01 Proceedings of the 4th International Workshop on Practice and Theory in Public Key Cryptography: Public Key Cryptography
Hardware architectures for public key cryptography
Integration, the VLSI Journal
IEEE Transactions on Computers
Fast factorization architecture in soft-decision Reed-Solomon decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-complexity versatile finite field multiplier in normal basis
EURASIP Journal on Applied Signal Processing
A multiplier to enhance the speed of encryption/decryption
ISP'06 Proceedings of the 5th WSEAS International Conference on Information Security and Privacy
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Extended sequential logic for synchronous circuit optimization and its applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast arithmetic architectures for public-key algorithms over Galois fields GF((2n)m)
EUROCRYPT'97 Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques
On efficient implementation of accumulation in finite field over GF(2m) and its applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI architecture for bit parallel systolic multipliers for special class of GF(2m) using dual bases
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Low-power and high-speed design of a versatile bit-serial multiplier in finite fields GF(2m)
Integration, the VLSI Journal
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Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to E.R. Berlekamp (1982); the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features that apply most suitably in particular areas. They are implemented on silicon chips with NMOS technology so that the multiplier most desirable for VLSI implementation can readily be ascertained.