A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases
IEEE Transactions on Computers
Decoding of Reed Solomon codes beyond the error-correction bound
Journal of Complexity
A displacement approach to efficient decoding of algebraic-geometric codes
STOC '99 Proceedings of the thirty-first annual ACM symposium on Theory of computing
High-speed VLSI architectures for the AES algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved decoding of Reed-Solomon and algebraic-geometry codes
IEEE Transactions on Information Theory
Efficient decoding of Reed-Solomon codes beyond half the minimum distance
IEEE Transactions on Information Theory
Efficient root-finding algorithm with application to list decoding of algebraic-geometric codes
IEEE Transactions on Information Theory
Algebraic soft-decision decoding of Reed-Solomon codes
IEEE Transactions on Information Theory
Partial parallel factorization in soft-decision Reed-Solomon decoding
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
High-speed interpolation architecture for soft-decision decoding of Reed-Solomon codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-latency factorization architecture for algebraic soft-decision decoding of Reed-Solomon codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reduced complexity interpolation architecture for soft-decision reed-solomon decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modified Low-Complexity Chase Soft-Decision Decoder of Reed---Solomon Codes
Journal of Signal Processing Systems
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Reed-Solomon (RS) codes are among the most widely utilized block error-correcting codes in modern communication and computer systems. Compared to its hard-decision counterpart, soft-decision decoding offers considerably higher error-correcting capability. The recent development of soft-decision RS decoding algorithms makes their hardware implementations feasible. Among these algorithms, the Koetter-Vardy (KV) algorithm can achieve substantial coding gain for high-rate RS codes, while maintaining a polynomial complexity with respect to the code length. In the KV algorithm, the factorization step can consume a major part of the decoding latency. A novel architecture based on root-order prediction is proposed in this paper to speed up the factorization step. As a result, the time-consuming exhaustive-search-based root computation in each iteration level, except the first one, of the factorization step is circumvented with more than 99% probability. Using the proposed architecture, a speedup of 141% can be achieved over prior efforts for a (255, 239) RS code, while the area consumption is reduced to 31.4%.