Decoding of Reed Solomon codes beyond the error-correction bound
Journal of Complexity
Fast factorization architecture in soft-decision Reed-Solomon decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partial parallel factorization in soft-decision Reed-Solomon decoding
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Improved decoding of Reed-Solomon and algebraic-geometry codes
IEEE Transactions on Information Theory
Efficient decoding of Reed-Solomon codes beyond half the minimum distance
IEEE Transactions on Information Theory
Efficient root-finding algorithm with application to list decoding of algebraic-geometric codes
IEEE Transactions on Information Theory
Algebraic soft-decision decoding of Reed-Solomon codes
IEEE Transactions on Information Theory
Modified Low-Complexity Chase Soft-Decision Decoder of Reed---Solomon Codes
Journal of Signal Processing Systems
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Reed-Solomon (RS) codes are among the most widely utilized error-correcting codes in digital communication and storage systems. Among the decoding algorithms of RS codes, the recently developed Koetter-Vardy (KV) soft-decision decoding algorithm can achieve substantial coding gain, while has a polynomial complexity. One of the major steps of the KV algorithm is the factorization. Each iteration of the factorization mainly consists of root computations over finite fields and polynomial updating. To speed up the factorization step, a fast factorization architecture has been proposed to circumvent the exhaustive-search-based root computation from the second iteration level by using a root-order prediction scheme. Based on this scheme, a partial parallel factorization architecture was proposed to combine the polynomial updating in adjacent iteration levels. However, in both of these architectures, the root computation in the first iteration level is still carried out by exhaustive search, which accounts for a significant part of the overall factorization latency. In this paper, a novel iterative prediction scheme is proposed for the root computation in the first iteration level. The proposed scheme can substantially reduce the latency of the factorization, while only incurs negligible area overhead. Applying this scheme to a (255, 239) RS code, speedups of 36% and 46% can be achieved over the fast factorization and partial parallel factorization architectures, respectively.