A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases
IEEE Transactions on Computers
A dual basis bit-serial systolic multiplier for GF(2m)
Integration, the VLSI Journal
Finite field inversion over the dual basis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mastrovito Multiplier for All Trinomials
IEEE Transactions on Computers
Fast Algorithms for Digital Signal Processing
Fast Algorithms for Digital Signal Processing
Error-Control Coding for Data Networks
Error-Control Coding for Data Networks
GF(2m) Multiplication and Division Over the Dual Basis
IEEE Transactions on Computers
A digit-serial multiplier for finite field GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography
IEEE Transactions on Computers
Systolic Multipliers for Finite Fields GF(2m)
IEEE Transactions on Computers
Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m)
IEEE Transactions on Computers
Bit-serial Reed - Solomon encoders
IEEE Transactions on Information Theory
Hi-index | 0.00 |
This paper presents the efficient VLSI architecture for bit parallel systolic multiplication over dual base for trinomial and pentanomial inGF(2m)for effective use in RS decoders. This architecture supports pipelining. Here irreducible trinomial of form p(x)=xm+xn+1 and pentanomial of the form p(x) = xm+xk+2+ xk+1+xk+1 generate the fields in GF(2m).For ECC algorithms, NIST recommends the five reduction polynomials which are either trinomial or pentanomial. Since the systolic multiplier has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. For trinomial, the systolic structure of proposed bit parallel dual multipliers requires only m2two inputs AND gates and at most (m2-1) two inputs EXOR gates. For pentanomial, it requires only m2two inputs AND gates and (m2+3m-3)two inputs EXOR gates. The proposed multipliers have clock cycle latency of m. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. This architecture can also operate over both the dual-base and polynomial base.