VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Introduction to finite fields and their applications
Introduction to finite fields and their applications
A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases
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Optimal normal bases in GF(pn)
Discrete Applied Mathematics
A VLSI Architecture for Fast Inversion in GF(2/sup m/)
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Systolic Gaussian Elimination Over GF(p) with Partial Pivoting
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Bit serial multiplication in finite fields
SIAM Journal on Discrete Mathematics
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Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)
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New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases
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High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m)
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Efficient scalable VLSI architecture for Montgomery inversion in GF(p)
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A Generalized Method for Constructing Subquadratic Complexity GF(2^k) Multipliers
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Low-complexity bit-parallel multiplier over GF(2m) using dual basis representation
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Low-complexity bit-parallel dual basis multipliers using the modified Booth's algorithm
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Combined circuit architecture for computing normal basis and Montgomery multiplications over GF(2m)
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| Hi-index | 15.04 |
In this paper an algorithm for GF(2m) multiplication/division is presented and a new, more generalized definition of duality is proposed. From these the bit-serial Berlekamp multiplier is derived and shown to be a specific case of a more general class of multipliers. Furthermore, it is shown that hardware efficient, bit-parallel dual basis multipliers can also be designed. These multipliers have a regular structure, are easily extended to different GF(2m) and hence suitable for VLSI implementations. As in the bit-serial case these bit-parallel multipliers can also be hardwired to carry out constant multiplication. These constant multipliers have reduced hardware requirements and are also simple to design. In addition, the multiplication/division algorithm also allows a bit-serial systolic finite field divider to be designed. This divider is modular, independent of the defining irreducible polynomial for the field, easily expanded to different GF(2m) and its longest delay path is independent of m.