VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
VLSI array processors
A VLSI Architecture for Fast Inversion in GF(2/sup m/)
IEEE Transactions on Computers
Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)
IEEE Transactions on Computers - Special issue on computer arithmetic
Polynomial and matrix computations (vol. 1): fundamental algorithms
Polynomial and matrix computations (vol. 1): fundamental algorithms
On Computing Multiplicative Inverses in GF(2/sup m/)
IEEE Transactions on Computers
A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2/sup m/)
IEEE Transactions on Computers
GF(2m) Multiplication and Division Over the Dual Basis
IEEE Transactions on Computers
A New Construction of Massey-Omura Parallel Multiplier over GF(2^{m})
IEEE Transactions on Computers
Hardware architectures for public key cryptography
Integration, the VLSI Journal
Systolic architectures for inversion/division using AB2 circuits in GF(2m)
Integration, the VLSI Journal
New Systolic Architectures for Inversion and Division in GF(2^m)
IEEE Transactions on Computers
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m)
IEEE Transactions on Computers
Efficient scalable VLSI architecture for Montgomery inversion in GF(p)
Integration, the VLSI Journal
IEEE Transactions on Computers
Computers and Electrical Engineering
C-testable bit parallel multipliers over GF(2m)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transition faults detection in bit parallel multipliers over GF(2m)
WSEAS Transactions on Circuits and Systems
IEEE Transactions on Circuits and Systems II: Express Briefs
Speeding up Euclid's GCD algorithm with no magnitude comparisons
International Journal of Information and Computer Security
Efficient hardware multiplicative inverters
ICISC'02 Proceedings of the 5th international conference on Information security and cryptology
Test generation in systolic architecture for multiplication over GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast inversion algorithm and low-complexity architecture over GF(2m)
CIS'05 Proceedings of the 2005 international conference on Computational Intelligence and Security - Volume Part II
Fast forth power and its application in inversion computation for a special class of trinomials
ICCSA'10 Proceedings of the 2010 international conference on Computational Science and Its Applications - Volume Part II
Integration, the VLSI Journal
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This paper presents two new systolic arrays to realize Euclid's algorithm for computing inverses and divisions in finite fields GF(2m) with the standard basis representation. One of these two schemes is parallel-in parallel-out, and the other is serial-in serial-out. The former employs O(m2) area complexity to provide the maximum throughput in the sense of producing one result every clock cycle, while the latter achieves a throughput of one result per m clock cycles using O(m· log2m) area complexity. Both of the proposed architectures are highly regular and, thus, well suited to VLSI implementation. As compared to existing related systolic architectures with the same throughput performance, the proposed parallel-in parallel-out scheme reduces the hardware complexity (and, thus, the area-time product) by a factor of O(m) and the proposed serial-in serial-out scheme by a factor of O(m/log2m).