Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
A VLSI Architecture for Fast Inversion in GF(2/sup m/)
IEEE Transactions on Computers
Principles of digital design
Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)
IEEE Transactions on Computers
Two systolic architectures for modular multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)
IEEE Transactions on Computers
Cryptography and data security
Cryptography and data security
On Computing Multiplicative Inverses in GF(2/sup m/)
IEEE Transactions on Computers
A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2/sup m/)
IEEE Transactions on Computers
Low complexity bit-parallel systolic architecture for computing C + AB2 over a class of GF(2m)
Integration, the VLSI Journal
Elliptic curve based hardware architecture using cellular automata
Mathematics and Computers in Simulation
Cellular automata architecture for elliptic curve cryptographic hardware
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part III
Modular divider for elliptic curve cryptographic hardware based on programmable CA
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part IV
Evolutionary hardware architecture for division in elliptic curve cryptosystems over GF(2n)
ICNC'05 Proceedings of the First international conference on Advances in Natural Computation - Volume Part III
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The current paper presents a new AB2 algorithm based on the MSB-first scheme using a standard basis representation of Galois fields, GF(2m). Thereafter, parallel-in parallel-out and serial-in serial-out systolic realizations for computing AB2 and inversion/division in GF(2m) are proposed on the basis of the new algorithm. The resulting architectures have a low hardware complexity and small latency when compared to conventional approaches. Furthermore, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI, produce a maximum throughput performance, and can also be utilized as the basic architecture for a cryptoprocessor.