VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
VLSI array processors
A VLSI Architecture for Fast Inversion in GF(2/sup m/)
IEEE Transactions on Computers
Cryptography and data security
Cryptography and data security
Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)
IEEE Transactions on Computers
New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)
IEEE Transactions on Computers
Architectures for Arithmetic over GF(2^m)
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Systolic architectures for inversion/division using AB2 circuits in GF(2m)
Integration, the VLSI Journal
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m)
IEEE Transactions on Computers
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
IEEE Transactions on Circuits and Systems II: Express Briefs
High-Speed hardware implementation of rainbow signature on FPGAs
PQCrypto'11 Proceedings of the 4th international conference on Post-Quantum Cryptography
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A new serial-in serial-out systolic array is presented for performing the element inversion in GF(2/sup m/) with the standard basis representation. The architecture is highly regular, modular, nearest neighbor connected, and thus well suited to VLSI implementation, It has a latency of 7m-3 clock cycles and a throughput rate of one result per 2m)-1 clock cycles. This speed performance is much better than those of the previous implementations. Without change in hardware design, the proposed inversion array can be directly used for computing the division in GF(2/sup m/).