Fast hardware algorithm for division in GF(2m) based on the extended Euclid's algorithm with parallelization of modular reductions

Authors:
Katsuki Kobayashi;Naofumi Takagi
Affiliations:
Department of Information Engineering, Graduate School of Information Science, Nagoya University, Nagoya, Japan;Department of Information Engineering, Graduate School of Information Science, Nagoya University, Nagoya, Japan
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2009

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Abstract

We propose a fast hardware algorithm for division in GF(2m) based on the extended Enclid's algorithm. The algorithm requires only one iteration to perform the operations that correspond to the ones performed in two iterations of previously reported division algorithms. Since the algorithm performs modular reductions in parallel by changing the order of execution of the operations, a circuit based on this algorithm has almost the same critical path delay as the previously proposed ones. The circnit computes division in m clock cycles, whereas the previously proposed circnits take 2m - 1 or more clock cycles.