VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Introduction to finite fields and their applications
Introduction to finite fields and their applications
A New Bit-Serial Systolic Multiplier Over GF(2/sup m/)
IEEE Transactions on Computers
A VLSI Architecture for Fast Inversion in GF(2/sup m/)
IEEE Transactions on Computers
Systolic Gaussian Elimination Over GF(p) with Partial Pivoting
IEEE Transactions on Computers
Division-and-Accumulation over GF(2m)
IEEE Transactions on Computers
Novel Radix Finite Field Multiplier for GF(2^m)
Journal of VLSI Signal Processing Systems
Efficient Multiplier Architectures for Galois Fields GF(24n)
IEEE Transactions on Computers
Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)
IEEE Transactions on Computers
Low-Energy Digit-Serial/Parallel Finite Field Multipliers
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
Double-Basis Multiplicative Inversion Over GF(2m)
IEEE Transactions on Computers
New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)
IEEE Transactions on Computers
GF(2m) Multiplication and Division Over the Dual Basis
IEEE Transactions on Computers
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Hardware architectures for public key cryptography
Integration, the VLSI Journal
New Systolic Architectures for Inversion and Division in GF(2^m)
IEEE Transactions on Computers
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m)
IEEE Transactions on Computers
A digit-serial multiplier for finite field GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An alternative approach to modulo-multiplication for finite fields using the Itoh-Tsujii algorithm
MATH'05 Proceedings of the 7th WSEAS International Conference on Applied Mathematics
IEEE Transactions on Circuits and Systems II: Express Briefs
A compact and fast division architecture for a finite field GF(2m)
ICCSA'03 Proceedings of the 2003 international conference on Computational science and its applications: PartI
On efficient implementation of accumulation in finite field over GF(2m) and its applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An alternative approach to modulo-multiplication for finite fields using the Itoh-Tsujii algorithm
AEE'05 Proceedings of the 4th WSEAS international conference on Applications of electrical engineering
Design of a variable key length cryptographic processor
AEE'05 Proceedings of the 4th WSEAS international conference on Applications of electrical engineering
An alternative approach to modulo-multiplication for finite fields using the Itoh-Tsujii algorithm
ICAI'05/MCBC'05/AMTA'05/MCBE'05 Proceedings of the 6th WSEAS international conference on Automation & information, and 6th WSEAS international conference on mathematics and computers in biology and chemistry, and 6th WSEAS international conference on acoustics and music: theory and applications, and 6th WSEAS international conference on Mathematics and computers in business and economics
A novel arithmetic unit over GF(2m) for low cost cryptographic applications
HPCC'05 Proceedings of the First international conference on High Performance Computing and Communications
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A systolic structure for bit-serial division over the field GF(2/sup m/) is developed. Consideration is given to avoid global data communications and dependency of the time step duration on m. This is important for applications where the value of m is large. The divider requires only three basic processors and one simple control signal and its circuit and time complexities are proportional to m/sup 2/ and m, respectively. It does not depend on the irreducible polynomial and can be expanded easily. Moreover, with m additional simple processors, a bit-serial systolic multiplier is developed which uses part of the divider structure. This is advantageous from the implementation point of view, as both the divider and multiplier can be fabricated on a single chip, resulting in a reduction of area.