Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)
IEEE Transactions on Computers - Special issue on computer arithmetic
Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)
IEEE Transactions on Computers
Double-Basis Multiplicative Inversion Over GF(2m)
IEEE Transactions on Computers
New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)
IEEE Transactions on Computers
High-speed architectures for Reed-Solomon decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cryptography and data security
Cryptography and data security
On Computing Multiplicative Inverses in GF(2/sup m/)
IEEE Transactions on Computers
EDTC '97 Proceedings of the 1997 European conference on Design and Test
High-speed systolic architectures for finite field inversion and division
Proceedings of the 14th ACM Great Lakes symposium on VLSI
High-speed systolic architectures for finite field inversion and division
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Area-efficient two-dimensional architectures for finite field inversion and division
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
High-speed systolic architectures for finite field inversion
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Integration, the VLSI Journal
Computers and Electrical Engineering
Fast elliptic curve cryptography on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Complexity analysis of Reed-Solomon decoding over GF(2m) without using syndromes
EURASIP Journal on Wireless Communications and Networking - Advances in Error Control Coding Techniques
IEEE Transactions on Circuits and Systems II: Express Briefs
High-speed systolic architectures for finite field inversion
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
FPGA implementation of highly parallelized decoder logic for network coding (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Design and comparison of NML systolic architectures
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
A high-performance unified-field reconfigurable cryptographic processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast forth power and its application in inversion computation for a special class of trinomials
ICCSA'10 Proceedings of the 2010 international conference on Computational Science and Its Applications - Volume Part II
Design and evaluation of random linear network coding Accelerators on FPGAs
ACM Transactions on Embedded Computing Systems (TECS)
Reconfigurable and parallelized network coding decoder for VANETs
Mobile Information Systems
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We present two systolic architectures for inversion and division in GF(2^m)based on a modified extended Euclidean algorithm. Our architectures are similar to those proposed by others in that they consist of two-dimensional arrays of computing cells and control cells with only local intercell connections and have O(m^2) area-time product. However, in comparison to similar architectures, both our architectures have critical path delays that are smaller, gate counts that range from being considerably smaller to only slightly larger, and latencies that are identical for inversion but somewhat larger for division. One architecture uses an adder or an (m + 1)-bit ring counter inside each control cell, while the other architecture distributes the ring counters into the computing cells, thereby reducing each control cell to just two gates.