New Systolic Architectures for Inversion and Division in GF(2^m)
IEEE Transactions on Computers
Clocking structures and power analysis for nanomagnet-based logic devices
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Computer
A VLSI architecture for image registration in real time
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fabrication Variations and Defect Tolerance for Nanomagnet-Based QCA
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
System-level energy and performance projections for nanomagnet-based logic
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
On-Chip Clocking for Nanomagnet Logic Devices
IEEE Transactions on Nanotechnology
Experimental Demonstration of Fanout for Nanomagnetic Logic
IEEE Transactions on Nanotechnology
A Reconfigurable PLA Architecture for Nanomagnet Logic
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Nanomagnet Logic (NML) is a device architecture that utilizes the magnetization of nano-scale magnets to perform logical operations. NML has been experimentally demonstrated and operates at room temperature. Because the nanomagnets are non-volatile, as data flows through a circuit, it is inherently pipelined. This feature makes NML an excellent fit for systolic architectures, which could enable low-power, high-throughput systems that can address a variety of application-level tasks. When considering possible NML systolic systems, the underlying systolic clocking scheme affects both architectural design and performance. In this paper we explore these issues in the context of two NML designs for convolution. One design is based on a 3-phase clocking scheme and uni-directional dataflow, and another is based on a 2-phase clocking scheme and bi-directional dataflow. We compare the two NML systolic designs in terms of area, delay, and energy. We also compare the NML and CMOS implementations of the design in terms of energy and delay. Results are supported by physical level simulation.