Exploring and exploiting wire-level pipelining in emerging technologies
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Eliminating wire crossings for molecular quantum-dot cellular automata implementation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Using CAD to shape experiments in molecular QCA
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Clocking structures and power analysis for nanomagnet-based logic devices
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Computer
Fabrication Variations and Defect Tolerance for Nanomagnet-Based QCA
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Ultra low-power neural inspired addition: when serial might outperform parallel architectures
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
Design and comparison of NML systolic architectures
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Performance and Energy Impact of Locally Controlled NML Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A Reconfigurable PLA Architecture for Nanomagnet Logic
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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This paper examines how realistic implementations of the drive circuitry needed to control circuit elements made from nano-scale magnets can affect system-level energy and performance. Expected non-uniform clock fields, clock field discontinuities and out-of-plane fields are all considered. We find that realistic fabrication mechanisms should not inhibit logical correctness and that this technology appears capable of outperforming low power CMOS equivalents with similar energy requirements — and paths to additional energy savings exist.