Ultra low-power neural inspired addition: when serial might outperform parallel architectures

Authors:
Valeriu Beiu;Asbjørn Djupdal;Snorre Aunet
Affiliations:
School of Electrical Engineering and Computer Science, Washington State University;Department of Computer Science and Information Technology, Norwegian University of Science and Technology, Norway;Department of Informatics, University of Oslo, Norway
Venue:
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
Year:
2005

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Abstract

In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when operating in subthreshold at 100nm and 70nm. These are targeted for ultra low power consumption applications. The elementary gates used are threshold logic gates (perceptrons). Simulations have been performed both with and without considering the delay on the wires. These simulations confirm that wires play a significant role, reducing the speed advantage of the parallel adder (over the serial one) from 4.5x to 2.2–2.4x. A promising result is that the speed of both adders improves more than 10x when migrating from 100nm to 70nm. The full adder based on threshold logic gates (used in the ripple carry adder) improves on previously known full adders, achieving 1.6fJ when operated at 200mV in 120nm CMOS. Finally, the speed of the parallel adder can be matched by the serial adder when operating at only 10–20% higher Vdd, while still requiring less power and energy.