Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Adaptive filter theory (3rd ed.)
Adaptive filter theory (3rd ed.)
Low-power adaptive filter architectures via strength reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Ultra-low power digital subthreshold logic circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Robust ultra-low power sub-threshold DTMOS logic
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Variations-aware low-power design with voltage scaling
Proceedings of the 42nd annual Design Automation Conference
Analysis and mitigation of variability in subthreshold design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Proceedings of the 43rd annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2006 international symposium on Low power electronics and design
Utilizing reverse short channel effect for optimal subthreshold circuit design
Proceedings of the 2006 international symposium on Low power electronics and design
Logic circuits operating in subthreshold voltages
Proceedings of the 2006 international symposium on Low power electronics and design
Energy optimality and variability in subthreshold design
Proceedings of the 2006 international symposium on Low power electronics and design
Reverberation canceling wireless aid for hearing impaired
Analog Integrated Circuits and Signal Processing
Variations-aware low-power design and block clustering with voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Utilizing reverse short-channel effect for optimal subthreshold circuit design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-power parallel design of discrete wavelet transform using subthreshold voltage technology
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Stack sizing for optimal current drivability in subthreshold in circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-efficient subthreshold processor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic synthesis of near-threshold circuits with fine-grained performance tunability
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System energy minimization via joint optimization of the DC-DC converter and the core
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Ultra low-power neural inspired addition: when serial might outperform parallel architectures
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
Hybrid super/subthreshold design of a low power scalable-throughput FFT architecture
Transactions on High-Performance Embedded Architectures and Compilers IV
Sub µW noise reduction for CIC hearing aids
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present an ultra-low-power, delayed least mean square (DLMS) adaptive filter operating in the subthreshold region for hearing aid applications. Subthreshold operation was accomplished by using a parallel architecture with pseudo nMOS logic style. The parallel architecture enabled us to operate the system at a lower clock rate and reduced supply voltage while maintaining the same throughput. Pseudo nMOS logic operating in the subthreshold region (subpseudo nMOS) provided better power-delay product than subthreshold CMOS (sub-CMOS) logic. Simulation results show that the DLMS adaptive filter can operate at 22 kHz using a 400-mV supply voltage to achieve 91% improvement in power compared to a nonparallel, CMOS implementation. To validate the robust operation of subthreshold logics, a 0.35 µm, 23.1 kHz, 21.4 nW, 8 × 8 carry save array multiplier test chip was fabricated where an adaptive body biasing scheme is used for compensating process, supply and temperature variations. The test chip showed stable operation at a supply voltage of 0.30 V, which is even lower than the threshold voltages of the pMOS (0.82 V) and nMOS (0.67 V) transistors.