Logic circuits operating in subthreshold voltages

Authors:
Jabulani Nyathi;Brent Bero
Affiliations:
Washington State University, Pullman, WA;Washington State University, Pullman, WA
Venue:
Proceedings of the 2006 international symposium on Low power electronics and design
Year:
2006

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Abstract

In this paper different logic circuit families operating in the subthreshold region are analyzed. Their performance in terms of power and speed are of particular interest. The study complements existing work that has reported static CMOS circuit performance under different body biasing schemes in the subthreshold region. Further it offers assurances on noise margins with scaling going beyond the 100 nm technology node. Simulations have been performed at the 180 nm technology node using a 6 metal layer TSMC process. A tunable body biasing scheme that allows bulk CMOS circuits to operate efficiently at subthreshold as well as above threshold voltages is introduced. The scheme improves a five-stage NAND ring oscillator switching speed 6X better than the static CMOS configuration while dissipating 18 % less power.