Ultra-low power digital subthreshold logic circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Logic circuits operating in subthreshold voltages
Proceedings of the 2006 international symposium on Low power electronics and design
A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
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Power is a significant design constraint for implementing efficient portable biomedical applications. Operating transistors in the subthreshold region can significantly reduce power consumption; it, however, also reduces performance. While this performance reduction can be significant in many applications, the low frequency nature of biosignals makes subthreshold region a good candidate for implementing biomedical applications. In this work, we investigate the feasibility of designing a specialized FPGA for implementing portable biomedical applications. In particular, we perform a case study on the performance of the Burg algorithm, a widely used biomedical signal processing algorithm, to determine the minimum operating frequency required for the processing of biosignals in real time. Based on the requirement, the trade-off between power consumption and performance is measured for FPGA routing resources operating in the subthreshold region. It is found that operating FPGA routing resources in the subthreshold region can significantly reduce power consumption while allowing the Burg algorithm to operate in real time. For the 32nm Predictive Technology Model studied in this work, we observed a power reduction of 197.7times (which corresponds to a power-delay-product reduction of 10.78times) for operating FPGA routing tracks in the subthreshold region under a supply voltage of 0.4V. Under this voltage, the FPGA can operate at 2.0MHz while allowing signals to propagate unregistered through 45 routing tracks. Furthermore, the 2.0MHz operating frequency meets the real-time requirement of the Burg algorithm for processing 20,000 samples per second.