MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
JouleTrack: a web based tool for software energy profiling
Proceedings of the 38th annual Design Automation Conference
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Design methodology and optimization strategy for dual-VTH scheme using commercially available tools
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Leakage control with efficient use of transistor stacks in single threshold CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
Statistical estimation of leakage current considering inter- and intra-die process variation
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2003 international symposium on Low power electronics and design
A low power approach to system level pipelined interconnect design
Proceedings of the 2004 international workshop on System level interconnect prediction
Evaluation of low-leakage design techniques for field programmable gate arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Leakage-and crosstalk-aware bus encoding for total power reduction
Proceedings of the 41st annual Design Automation Conference
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment
Proceedings of the 41st annual Design Automation Conference
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation
Proceedings of the 2004 international symposium on Low power electronics and design
Low power design using dual threshold voltage
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Enabling on-chip diversity through architectural communication design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage current estimation of CMOS circuit with stack effect
Journal of Computer Science and Technology - Special issue on computer graphics and computer-aided design
Combining low-leakage techniques for FPGA routing design
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Enhanced leakage reduction Technique by gate replacement
Proceedings of the 42nd annual Design Automation Conference
An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
Energy Optimization of Subthreshold-Voltage Sensor Network Processors
Proceedings of the 32nd annual international symposium on Computer Architecture
Low-power techniques for network security processors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal module and voltage assignment for low-power
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical technology mapping for parametric yield
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A combined gate replacement and input vector control approach for leakage current reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal simultaneous module and multivoltage assignment for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Charge recycling in MTCMOS circuits: concept and analysis
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Logic circuits operating in subthreshold voltages
Proceedings of the 2006 international symposium on Low power electronics and design
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Tartan: evaluating spatial computation for whole program execution
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Thermal-aware high-level synthesis based on network flow method
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Sizing and placement of charge recycling transistors in MTCMOS circuits
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Leakage current optimization techniques during test based on don't care bits assignment
Journal of Computer Science and Technology
A low-power parallel design of discrete wavelet transform using subthreshold voltage technology
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
System-level mitigation of WID leakage power variability using body-bias islands
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A power-aware algorithm for the design of reconfigurable hardware during high level placement
International Journal of Knowledge-based and Intelligent Engineering Systems - Adaptive Hardwarel / Evolvable Hardware
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hybrid nano/CMOS dynamically reconfigurable system—Part I: Architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Application-driven voltage-island partitioning for low-power system-on-chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sleep transistor sizing for leakage power minimization considering charge balancing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ABRM: adaptive β-ratio modulation for process-tolerant ultradynamic voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power and high speed multiplier design with row bypassing and parallel architecture
Microelectronics Journal
Energy minimization for real-time systems with non-convex and discrete operation modes
Proceedings of the Conference on Design, Automation and Test in Europe
Technique for controlling power-mode transition noise in distributed sleep transistor network
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Bus encoding for total power reduction using a leakage-aware buffer configuration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Genetic algorithm based fine-grain sleep transistor insertion technique for leakage optimization
ICNC'06 Proceedings of the Second international conference on Advances in Natural Computation - Volume Part I
Temperature aware statistical static timing analysis
Proceedings of the International Conference on Computer-Aided Design
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs
Proceedings of the International Conference on Computer-Aided Design
Leakage power characterization considering process variations
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Microprocessors & Microsystems
Hybrid super/subthreshold design of a low power scalable-throughput FFT architecture
Transactions on High-Performance Embedded Architectures and Compilers IV
Hierarchical power management for adaptive tightly-coupled processor arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Functional verification of low power designs at RTL
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Optimization for real-time systems with non-convex power versus speed models
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
System-level leakage variability mitigation for MPSoC platforms using body-bias islands
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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As technology scales, subthreshold leakage currents grow exponentially and become an increasingly large component of total power dissipation. CAD tools to help model and manage subthreshold leakage currents will be needed for developing ultra low power and high performance integrated circuits. This paper gives an overview of current research to control leakage currents, with an emphasis on areas where CAD improvements will be needed. The first part of the paper explores techniques to model subthreshold leakage currents at the device, circuit, and system levels. Next, circuit techniques such as source biasing, dual Vt partitioning, MTCMOS, and VTCMOS are described. These techniques reduce leakage currents during standby states and minimize power consumption. This paper also explores ways to reduce total active power by limiting leakage currents and optimally trading off between dynamic and leakage power components.