Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS

Authors:
Siva Narendra;Vivek De;Shekhar Borkar;Dimitri Antoniadis;Anantha Chandrakasan
Affiliations:
Massachusetts Institute of Technology, Cambridge, MA and Intel Laboratories, Hillsboro, OR;Intel Laboratories, Hillsboro, OR;Intel Laboratories, Hillsboro, OR;Massachusetts Institute of Technology, Cambridge, MA;Massachusetts Institute of Technology, Cambridge, MA
Venue:
Proceedings of the 2002 international symposium on Low power electronics and design
Year:
2002

Citing 3
Cited 34

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Abstract

The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, control switching power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. With threshold voltage scaling sub-threshold leakage power is expected to become a significant portion of the total power in future CMOS systems. Therefore, it becomes crucial to predict sub-threshold leakage power of such systems. In this paper, we present a sub-threshold leakage power prediction model that takes into account within-die threshold voltage variation. Statistical measurements of 32-bit microprocessors in 0.18 mm CMOS confirms that the mean error of the model to be 4%. Comparisons of this model to two other existing models that do not take within-die threshold voltage variation into account are also presented.