Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
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IEEE Micro
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ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2004 international symposium on Low power electronics and design
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Robust extraction of spatial correlation
Proceedings of the 2006 international symposium on Physical design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation
Proceedings of the 2006 international symposium on Low power electronics and design
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Foundations and Trends in Electronic Design Automation
A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we present an efficient technique for finding the mean and variance of the full-chip leakage of a candidate design, while considering logic structures and both die-to-die and within-die (WID) process variations, and taking into account the spatial correlation due to WID variations. Our model uses a "random-gate" concept to capture high-level characteristics of a candidate chip design, which are sufficient to determine its leakage. These high-level characteristics include information about the process, the standard cell library, and expected design characteristics. We show empirically that, for large gate count, the set of all chip designs that share the same high-level characteristics have approximately the same leakage, with very small error. Therefore, our model can be used as either an early or a late estimator of leakage, with high accuracy. In its simplest form, we show that full-chip-leakage estimation reduces in finding the area under a scaled version of the WID channel length autocorrelation function, which can be done in constant time.