Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization
Integration, the VLSI Journal
Full-chip model for leakage-current estimation considering within-die correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical leakage estimation based on sequential addition of cell leakage currents
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A fast and accurate statistical method that estimates at gate level the leakage power consumption of CMOS digital circuits is demonstrated. Means, variances and correlations of logic gate leakages are extracted at library characterization step, and used for subsequent circuit statistical computation. In this paper, the methodology is applied to an eleven thousand cells ST test IP. The circuit leakage analysis computation time is 400 times faster than a single fast-Spice corner analysis, while providing coherent results.