RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
A two moment RC delay metric for performance optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Selective gate-length biasing for cost-effective runtime leakage control
Proceedings of the 41st annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
Tutorial 2: Leakage Issues in IC Design: Trends, Estimation, and Avoidance
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient adaptive voltage scaling system through on-chip critical path emulation
Proceedings of the 2004 international symposium on Low power electronics and design
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Advanced timing analysis based on post-OPC extraction of critical dimensions
Proceedings of the 42nd annual Design Automation Conference
RADAR: RET-aware detailed routing using fast lithography simulations
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Variability in sub-100nm SRAM designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Design at the end of the silicon roadmap
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast and efficient phase conflict detection and correction in standard-cell layouts
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Standard cell library optimization for leakage reduction
Proceedings of the 43rd annual Design Automation Conference
Ultra low-cost defect protection for microprocessor pipelines
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
IEEE Design & Test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical interconnect metrics for physical-design optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reducing process variation impact on replica-timed static random access memory sense timing
Integration, the VLSI Journal
Self-timed SRAM for energy harvesting systems
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
An on-chip all-digital PV-monitoring architecture for digital IPs
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
The magic rule of tiles: virtual delay insensitivity
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Embedding statistical tests for on-chip dynamic voltage and temperature monitoring
Proceedings of the 49th Annual Design Automation Conference
A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Power yield analysis under process and temperature variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
UDSM trends comparison: from technology roadmap to UltraSparc Niagara2
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the optimality of K longest path generation algorithm under memory constraints
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Variation is a significant concern in nanometer-scale CMOS due to manufacturing equipment being pushed to fundamental limits, particularly in lithography. In this paper, we review recent work in coping with variation, through both improved analysis and optimization. We describe techniques based on integrated circuit manufacturing, circuit design strategies, and mathematics and statistics. We then go on to discuss trends in this area, and a future technology outlook with an eye towards circuit and CAD-solutions to growing levels of variation in underlying device technologies.