Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation

Authors:
Tom Chen;Samuel Naffziger
Affiliations:
Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, CO;System VLSI Technology Division, Hewlett Packard Company, Fort Collins, CO
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Year:
2003

Citing 5
Cited 43

A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
On gate level power optimization using dual-supply voltages

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing Yield Estimation from Static Timing Analysis

ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design

Statistical optimization of leakage power considering process variations using dual-Vth and sizing

Proceedings of the 41st annual Design Automation Conference
Technology exploration for adaptive power and frequency scaling in 90nm CMOS

Proceedings of the 2004 international symposium on Low power electronics and design
Optimization of Individual Well Adaptive Body Biasing (IWABB) Using a Multiple Objective Evolutionary Algorithm

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
New ECC for Crosstalk Impact Minimization

IEEE Design & Test
Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Nanometer scale technologies: device considerations

Nano, quantum and molecular computing
Ultralow-voltage, minimum-energy CMOS

IBM Journal of Research and Development - Advanced silicon technology
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A statistical framework for post-silicon tuning through body bias clustering

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ReCycle:: pipeline adaptation to tolerate process variation

Proceedings of the 34th annual international symposium on Computer architecture
Compiler-Directed Variable Latency Aware SPM Management to CopeWith Timing Problems

Proceedings of the International Symposium on Code Generation and Optimization
Statistical performance modeling and optimization

Foundations and Trends in Electronic Design Automation
Post silicon power/performance optimization in the presence of process variations using individual well-adaptive body biasing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Variability-driven module selection with joint design time optimization and post-silicon tuning

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip

Proceedings of the 18th ACM Great Lakes symposium on VLSI
Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --

Proceedings of the 18th ACM Great Lakes symposium on VLSI
Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization

Integration, the VLSI Journal
Variation-aware gate sizing and clustering for post-silicon optimized circuits

Proceedings of the 13th international symposium on Low power electronics and design
Error-resilient low-power Viterbi decoders

Proceedings of the 13th international symposium on Low power electronics and design
Process variation aware issue queue design

Proceedings of the conference on Design, automation and test in Europe
Error-resilient motion estimation architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Facelift: Hiding and slowing down aging in multicores

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
EVAL: Utilizing processors with variation-induced timing errors

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation

Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Frequency and yield optimization using power gates in power-constrained designs

Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Selective wordline voltage boosting for caches to manage yield under process variations

Proceedings of the 46th Annual Design Automation Conference
Voltage binning under process variation

Proceedings of the 2009 International Conference on Computer-Aided Design
Verifying VLSI Circuits

ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
Error-resilient low-power Viterbi decoder architectures

IEEE Transactions on Signal Processing
Rapid design space exploration using legacy design data and technology scaling trend

Integration, the VLSI Journal
Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels

Proceedings of the Conference on Design, Automation and Test in Europe
Benefits and barriers for probabilistic design

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Body bias voltage computations for process and temperature compensation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Structured analog circuit design and MOS transistor decomposition for high accuracy applications

Proceedings of the International Conference on Computer-Aided Design
Row-based FBB: A design-time optimization for post-silicon tunable circuits

Microelectronics Journal
Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry

Proceedings of the 49th Annual Design Automation Conference
Timing analysis with nonseparable statistical and deterministic variations
Accurate characterization of the variability in power consumption in modern mobile processors

HotPower'12 Proceedings of the 2012 USENIX conference on Power-Aware Computing and Systems
A statistical model of logic gates for Monte Carlo simulation including on-chip variations

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Energy attacks and defense techniques for wireless systems

Proceedings of the sixth ACM conference on Security and privacy in wireless and mobile networks
Hardware/software approaches for reducing the process variation impact on instruction fetches

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Fine-grain voltage tuned cache architecture for yield management under process variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Process variations as a percentage of nominal delay and power consumption are becoming more and more severe with continuing scaling of VLSI technology. The worsening process variation causes increased variability in performance, power, and reliability of VLSI circuits. Thus, performance and power consumption targets obtained during the design phase of VLSI circuits may significantly deviate from that of actual silicon resulting in significant yield losses. Adaptive body bias (ABB) has been shown to be an effective method of postsilicon tuning to reduce variability under the presence of process variation. Post silicon tuning can also be accomplished by using adaptive supply voltage (ASV). This paper compares the effectiveness of ABB and ASV in reducing variability and improving performance and power, and thus, yield.