Technology exploration for adaptive power and frequency scaling in 90nm CMOS

Authors:
Maurice Meijer;Francesco Pessolano;Jose Pineda de Gyvez
Affiliations:
Philips Research Laboratories, Eindhoven, The Netherlands;Philips Research Laboratories, Eindhoven, The Netherlands;Philips Research Laboratories, Eindhoven, The Netherlands
Venue:
Proceedings of the 2004 international symposium on Low power electronics and design
Year:
2004

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Abstract

In this paper we examine the expectations and limitations of design technologies such as adaptive voltage scaling (AVS) and adaptive body biasing (ABB) in a modern deep sub-micron process. To serve this purpose, a set of ring oscillators was fabricated in a 90nm triple-well CMOS technology. The analysis hereby presented is based on two ring oscillators running at 822MHz and 93MHz, respectively. Measurement results indicate that it is possible to reach 13.8x power savings by 3.4x frequency downscaling using AVS, 卤11% power and 卤8% frequency tuning at nominal conditions using ABB only, 22x power savings with 5x frequency downscaling by combining AVS and ABB, as well as 22x leakage reduction.